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Senior Design Quality and Reliability Lead for IP Ecosystem and Design Enablement

Company: Intel GmbH
Location: Hillsboro
Posted on: January 11, 2022

Job Description:

  • --- Senior Design Quality and Reliability Lead for IP Ecosystem and Design Enablement Hillsboro, OR Job ID: JR0187048 Job Category: Engineering Primary Location: Hillsboro, OR US Other Locations: US, Arizona, Phoenix;US, California, Santa Clara Job Type: Experienced Hire Senior Design Quality and Reliability Lead for IP Ecosystem and Design EnablementJob Description
    To support Intel IDM 2.0 and world-leading Intel Foundry Services (IFS) strategy, the Technology and Design Enablement Quality and Reliability group is looking for talents at different levels and in different areas to join this exciting journey to drive design enablement in quality and reliability areas with Ease of Use (EoU) features on Intel technology to build competitive design and IP ecosystem to meet external and internal customer needs for industry leadership. -The general reliability design enablement areas include but are not limited to DTCO (Technology-Design Co-Optimization), PDK (Process Design Kits), Hard and soft IP (Intellectual Property) ecosystem enablement, TFM (Tool/Flow/Methodology), DFR (Design for Reliability), PPA (Power Performance Area) and reliability co-optimization. -This senior position focuses on IP design and ecosystem enablement in the reliability area, level can vary depending on the qualification of the candidates. -This role will be responsible for but not limited to:
    • Lead and conduct a competitive analysis in technology and IP offering to be competitive across the industry. -
    • Define industry competitive Q&R requirements and business process for 3rd party IP to meet customer needs for different market segments such as commercial, automotive, etc. -
    • Q&R lead to participate and help define IP portfolio and roadmap including internal and 3rd Party IP with IFS to build a competitive and industry-leading IP ecosystem. -
    • Drive contract closure, review SOW (Statement of Work), and conduct review and sign-off as needed for Q&R requirements in SOW to meet IP quality and grading expectations in synch with overall IP roadmap and execution. -
    • Drive EDA tool and flow enablement and align with IP and EDA vendors to deliver competitive IP and TFM with EoU features to delight our customers.
      Qualifications

      You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:The candidate must possess at least one of the following degrees plus the years of experience determined for each degree in the areas specified below: 1. Master's degree in Electrical Engineering, Physics, or related fields. with 7+ years of experience in the below areas . 2. Ph .D. degree in Electrical Engineering, Physics, or related fields. with 5+ years of experience in the below areas. Areas of expertise:
      • Working with external customers or IP vendors on advanced analog, mixed-signal, memory IP design, and reliability validation for the different market segments, including reliability assessment, review, and sign-off, driving optimization, and trade-off as needed.
      • Industry reliability method and practice for IP and full-chip, and SOC (System on a Chip) design and validation.Preferred Qualifications:
        • Direct working experiences on 3rd party IP design on Foundry process and IP ecosystem enablement.
        • Deep understanding of industry design method, workflow, and reliability validation practices.
        • Extensive knowledge and experience on EDA tool/flow development and application on IP and SOC design, quality and reliability validation.
        • - Reliability physics, design for reliability for ESD (Electrostatic Discharge), LU (Latch-Up), Aging including BTI (Bias Temperature Instability) and HCI (Hot Carrier Injection), Electro-Migration, High Voltage design rule, EOS (Electrical Over-Stress), etc.
        • Design flow and EDA (Electronic Design Automation) tools for reliability simulation and validation in one or multiple areas. - Inside this Business Group
          As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the -Technology Development and Manufacturing Group -are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

          Other Locations

          US, Arizona, Phoenix;US, California, Santa Clara
          Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.


          Posting Statement

          All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Keywords: Intel GmbH, Hillsboro , Senior Design Quality and Reliability Lead for IP Ecosystem and Design Enablement, Other , Hillsboro, Oregon

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