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Platform Hard IP Integration PM

Company: Intel Corp.
Location: Hillsboro
Posted on: November 19, 2021

Job Description:

Platform Hard IP Integration PM Job Description In this position, you will be responsible for hard IP (HIP) integration specifications to enable and support efficient IP-SoC integration and maximize IP reuse across projects on a given technology node. Responsibilities of the role include, although not limited to: * Lead global IP integration spec workgroups with representatives from technology, design automation, SoC and IP design teams * Define requirements and drive alignment and ratification of IP physical and electrical integration specifications * Collaborate and align with stakeholders on the definition, implementation, and validation of IP signoff checks * Coordinate, manage, and prioritize new requirements and change requests across SoC and IP teams and other stakeholders * Document, present, publish, and maintain HIP integration specification documents The ideal candidate should exhibit the following behavioral traits: * Focused, self-driven, self-disciplined, flexible, motivated, meticulous, results-oriented, and innovative * Strong leadership, analysis, communication, presentation, and documentation skills * Willing to multitask, work independently and as a team player, and excel in a dynamic, fast-paced, and highly matrixed environment * Willing to collaborate, influence, manage, and drive tasks of broad scope and complexity across organizational boundaries Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate must have a Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 9+ years experience -OR- a Masters degree in Electrical Engineering, Computer Engineering, Computer Science or a related field with 6+ years experience in the following: * SoC integration challenges, IP collateral requirements, and IP integration * Industry standard ASIC and/or custom design and signoff on leading edge process technologies * Relevant industry standard EDA tools/flows for digital and/or analog design and signoff Preferred Qualifications: * Working experience of collaborating with process, design, and design automation teams Inside this Business Group The Design Engineering Group is a worldwide team responsible for the design, development, validation, and manufacturing of IPs and SOCs. Our mission is to deliver leadership products through groundbreaking innovations. Other Locations US, California, Santa Clara;US, Texas, Austin Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. USExperienced HireJR0180573HillsboroDesign Engineering Group

Keywords: Intel Corp., Hillsboro , Platform Hard IP Integration PM, Other , Hillsboro, Oregon

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