In this role responsibilities include, although are not limited
+ Perform logic design, Register Transfer Level (RTL) coding,
and simulation to generate cell libraries, functional units, and
subsystems for inclusion in full chip designs.
+ Participate in the development of Architecture and
Microarchitecture specifications for the Logic components.
+ Provide IP integration support to SoC customers and represents
+ Work on high-speed digital design and is targeted towards low
power optimized implementations of high speed IPs and interfaces
like DDRIO, Serial IO's,PLL's, Power Circuits.
+ Implement RTL in System Verilog, validating the design,
synthesizing the design and closing timing.
+ high-level Architecture through to the details of timing.
+ Work with specifications at multiple levels, including the HAS
and MAS (microarchitecture spec).
+ Balance design trade-offs with modularity, scalability, DFX
requirements, power, area, and performance.
Candidate must have a Bachelor's degree in Electrical
Engineering and 4+ years' experience - OR - a Master's degree in
Electrical Engineering and 3+ years' experience - OR - a PhD and 2+
years' experience in/with:
+ RTL level Digital IC Design using System Verilog and/or
+ Low power design,
+ Analog design concerns and driving to an optimal solution
between analog and digital designs
+ Pre-silicon and post-silicon validation.
1+ years' experience in/with:
+ Logic design using System Verilog
+ Micro-architecture trade-offs and documentation
+ Low-power design using UPF and clock gating
+ Multiple clock domain design
+ State machine design
+ Simulation and debug experience using VCS/Verdi
+ Synthesis and speed path debug
+ Perl / C-shell
**Inside this Business Group**
IP Engineering Group's (IPG) vision Build IPs that power Intel's
leadership products and power our customer's silicon. We want to
attract & retain talent who get joy in building high quality IP and
share our core belief that IP is fundamental to transforming
Intel's silicon design process. IPG's guiding principles will be
ensuring Quality (Zero Bugs), Customer Obsession (Delight our
Customers) and structured Problem Solving. We are a fearless
organization transforming IP development.
US, California, Santa Clara
All qualified applicants will receive consideration for
employment without regard to race, color, religion, religious
creed, sex, national origin, ancestry, age, physical or mental
disability, medical condition, genetic information, military and
veteran status, marital status, pregnancy, gender, gender
expression, gender identity, sexual orientation, or any other
characteristic protected by local law, regulation, or