As a member of the Advanced Design Library technology group in
TMG/DE, you will be at the vanguard of designing analog
foundational IP on leading edge Intel processes to meet density and
performance scaling goals of Intel CPU and SoC products. AD serves
as the design interface with the process development team, working
out key design/process interactions for all new processes.
You will be responsible for the pathfinding, design, Silicon
validation and support of primitive copy-exact analog foundational
IP that relate to Electrostatic Discharge (ESD) protection device
design and integration. These IPs include: ESD diodes, Power
clamps, analog transistors, resistors, capacitors, thermal sensing
devices and others.
Additional responsibilities include:
- Definition of copy-exact foundational IP in collaboration with
analog and I/O designers in product groups and AD to support ESD
- Balancing ESD protection needs against the performance impact
to the I/O designs.
- Working with process, device, and Q&R stake holders as part
of DTCO to co-optimize design and process modeling and rules.
- Designing schematics and layouts and characterizing them
through all PV, RV and ESD flows.
- Ensuring industry standard TFM and EDA support is enabled for
- Implementing test structures in Si to characterize performance
metrics and performing on-going updates based on latest silicon
simulation correlation learnings.
You must possess the below minimum qualifications to be
initially considered for this position. Preferred qualifications
are in addition to the minimum requirements and are considered a
plus factor in identifying top candidates. Experience listed below
would be obtained through a combination of your
schoolwork/classes/research and/or relevant previous job and/or
- Must possess MS EE or PhD
- 6+ months ESD fundamentals, semiconductor device physics
- Analog circuit design and simulation layout methodology and
interaction with EDA tool/flows
6+ months experience in the following areas:
- Coding skills in some language to improve work efficiency is a
- ESD protection methodology schemes.
- Semiconductor behavior under ESD conditions.
- Silicon characterization and silicon simulation
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make
every facet of semiconductor manufacturing state-of-the-art -- from
semiconductor process development and manufacturing, through yield
improvement to packaging, final test and optimization, and world
class Supply Chain and facilities support. Employees in the
Technology and Manufacturing Group are part of a worldwide network
of design, development, manufacturing, and assembly/test
facilities, all focused on utilizing the power of Moore's Law to
bring smart, connected devices to every person on Earth
US, California, Santa Clara
All qualified applicants will receive consideration for
employment without regard to race, color, religion, religious
creed, sex, national origin, ancestry, age, physical or mental
disability, medical condition, genetic information, military and
veteran status, marital status, pregnancy, gender, gender
expression, gender identity, sexual orientation, or any other
characteristic protected by local law, regulation, or