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Logic Validation Engineer

Company: Intel Corp.
Location: Hillsboro
Posted on: May 3, 2021

Job Description:

Logic Validation Engineer

Job Description

As a member of the Logic Design & Validation group within the Lead Vehicle Development group in Design Enablement you will be part of a team that develops the RTL models and pre-silicon validation tests for test chips on the next generation Intel silicon manufacturing process.

Your responsibilities would include:

  • Creating new digital, analog, and mixed-signal RTL models for new and existing designs
  • Running the Functional Equivalence Verification (FEV) flow to compare RTL to schematics
  • Owning the creation of pre-silicon validation test plans, formal SystemVerilog/UVM testbenches, and validation test cases
  • Owning RTL design of new digital systems ranging from design-for-test (DFT) on existing systems to novel designs to enable Power-Performance-Area (PPA) studies on next-generation technology nodes.

The ideal candidate should exhibit the following behavioral traits:

  • Motivated, driven, with sense of urgency and commitment to achieve targeted goals
  • Communication and problem-solving skills
  • Documentation, and presentation skills
  • Troubleshooting and analytical skills

This is an entry level position and compensation will be given accordingly.


You must possess minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

Minimum Requirements:

Candidate must possess a Master's degree in Electrical Engineering, Computer Engineering, or related fields of study with experience listed below or a Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with a minimum of 1+ years of experience in the following:

  • Digital design using Verilog and SystemVerilog
  • Performing Pre-Silicon Logic Validation at Unit level or Integration level
  • Experience with OVM/UVM test benches and verification concepts
  • Object Oriented Programing (OOP) in any programing language, preferably in SystemVerilog
  • SystemVerilog Assertions (SVA), their creation and application in closing validation coverage
  • Coverage-based verification and how to leverage for efficient validation closure

Preferred Requirements:

  • Experience with analog circuits and their interaction with digital systems
  • Experience in the Unified Power Format (UPF) specification
  • Experience with scripting and automation with languages such as Perl or Python


Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

USCollege GradJR0159646Hillsboro

Keywords: Intel Corp., Hillsboro , Logic Validation Engineer, Other , Hillsboro, Oregon

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