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DFT Lead and Site Manager

Company: Intel
Location: Hillsboro
Posted on: September 13, 2020

Job Description:

This site uses cookies for functionality, analytics, and advertising purposes as described in our Cookie and Similar Technologies Notice. To see what cookies we serve and set your preferences, please visit our Cookie Consent Tool. By continuing to use our website, you agree to our use of cookies. Design for Test Engineering Group (DTEG) is Intel's central Design for Test (DFT) organization driving DFT architectures, methodologies, IPs, and automation across Intel. As a member of the DTEG team, we're looking for passionate leader to manage the local team in Santa Clara/Oregon/Fort-Collins. Key responsibilities of the role include, although not limited to: Lead the activities and manage the local DTEG team. These activities include DFT architecture/methodology development and deployment, validation, fault grading, tools development, customers support, and more. Working with and supporting multiple IP/SoC design teams across different geographies, and as such requires strong collaboration and excellent written and verbal communication skills. Setting technical direction in one or more specific DFT areas. Setting priorities for the team, get results across boundaries, ensure an inclusive work environment, develop employees, and manage performance. Selecting, develop, and evaluate DFT engineers to ensure efficient operation. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum QualificationsCandidate must have a Bachelor's degree in Electrical Engineering or Computer Engineering and 9+ years of experience - OR - a Master's degree in Electrical Engineering or Computer Engineering and 6+ years of experience - OR - a PhD in Electrical Engineering or Computer Engineering and 4+ years of experience in: Understanding of various DFT techniques such as scan/ATPG, memory BIST, TAP architecture, fault grading, etc. Leading and building teams through setting goals, schedule and staging plans along with tracking and enabling execution for team. Influencing and collaborating with multiple teams across Intel Understanding of various DFT techniques such as Scan/ATPG, Memory BIST, IO DFT, etc. and a deep knowledge of relevant EDA vendor tools. Silicon enabling and debug solutions. Influencing and collaborating with multiple teams across Intel Inside this Business Group The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences. Other Locations US, California, Santa Clara;US, Colorado, Fort Collins Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....

Keywords: Intel, Hillsboro , DFT Lead and Site Manager, Other , Hillsboro, Oregon

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